中国科大学位与研究生教育
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多态处理器体系结构研究
多态处理器体系结构研究
教师介绍
Professor Li Tao received the M.E. degree from the Institute of Computer Technology of CAS, China, in 1978, and the PhD degree in computer science from UTAH, the U.S.A, in 1985. Now he is the Chief Engineer of “13115” Engineering Center of Shanxi Province, and the professor of Electronic Engineering Department of Xi’An University of Posts and Telecommunications. Professor Li Tao long been engaged in the field of integrated circuit research and development work, and successfully developed the CMTS and Cable router dedicated FPGA chips used in Motorola BSR1000 and BSR64000 series of high-speed routers. He had published over 20 articles in international journals, written chapters for seven books, written a book and published 60-70 articles in the International Conference. He had won the International Insight-2005 (IT Education) Annual Conference Best Paper Award (winning educational content is intelligent automatic generation of mathematical word problems) and the 1995 Annual Meeting of the International Oriental Language Processing Best Paper Award (winning content is self-learning neural tree pattern recognition software).

本讲教师:李涛
所属学科:工科
人  气:2118

课程介绍
【IC设计前沿技术系列讲座2013-14】 题目:Research of Architecture of Polymorphic Processor 时 间: 2013年8月14日(周三) 4:00-5:00 PM 地 点: 科大西区电四楼310会议室 报 告 人: 李涛 教授 主要内容:Today what is the popular heterogeneous parallel architecture is the CPU+GPU structure, which defers to the Amdahl’s Law of the parallel computing. While the parallel computing is the trend of computing solution, it is also the matter the integrated circuit has to cope with. CPU+GPU is, however, the only choice today because there is no other better way. Today CPU and GPU each does their own thing, no coincident operation has been developed between them.The lecture introduces the array processor structure of polymorphic processor. This structure can achieve data parallel logic (DLP), task parallel logic (TLP) and instruction parallel logic (ILP) on the parallel array processor. Furthermore these three important parallel processing modes can be seamlessly linked up with each other. Finally, this talk introduce a simulation development environment developed for this structure, and its FPGA validation methodology.
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