Professor and Vice Chair，UCLA Electrical Engineering Department Biography Jason C.S. Woo received the B.A.Sc. (Hons.) degree in engineering science from the University of Toronto, Canada, in 1981, and the M.S. and Ph.D. degrees in electrical engineering from Stanford University in 1982 and 1987, respectively. He joined the UCLA Electrical Engineering Department in 1987 and is currently a professor. Prof. Woo served on the IEEE IEDM program committee from 1989-1990 and 1994-1996, and was the publicity vice-chairman in 1992 and the publicity chairman in 1993. He is the workshop chairman and has been a technical committee member of the VLSI Technology Symposium since 1992. Since 1993, he has been on the IEEE SOI conference committee and was the technical program chairman for the conference in 1999. He has also been appointed recently to serve as the chair of IEEE Electronic Device Society ad hoc committee on short courses. He has authored or coauthored over 100 papers in technical
Chap 1. Short Channel CMOS Devices ( 6 hs)
1.1 Summary of Long Channel CMOS Device Characteristics .
1.1.1 D.C I-V Characteristics .
1.1.2 CMOS Voltage Gain Stage .
1.1.3 Weak Inversion (Subthreshold) Characteristics.
1.2 CMOS Device Scaling and ITRS Road Map.
1.3 Short channel effects ( SCE).
1.3.1 Reduction of Vth in Short Channel MOSFET .
1.3.2 Drain-Induced Barrier Lowering (DIBL) ,
1.3.3Channel Length Dependence of Vth .
1.3.4 Velocity Saturation and Short Channel Device
I-V characteristics .
1.4 MOS Device Design .
1.4.1 MOSFET Scaling
Constant Field Scaling scheme
Generalized Scaling scheme
1.4.2 Non-uniform Doping and Retrograde Well Doping
1.4.3 Shallow s/d Junctions , s/d Extension, and Raised s/d
1.5 CMOS Devices in Ballistic Transport Limit
1.5.1 Ballistic Transport Limit
1.5.2 Quasi-Ballistic Transport and Back-Scattering Coefficient
1.5.3 Velocity Overshoot in Short Channel Devices
1.6 Summary of I-V Characteristics of CMOS Transistors
Chap 2. New Physical Effects ( 3 hs )
2.1 Auger Recombination and Impact Ionization .
2.2 Carrier Quantization in a Quantum Well.
2.2.1 Carrier Quantization.
2.2.2 Density of States in Quantum Well .
2.2.3The Impact of Carrier Quantization in MOS Device
2.3 Quantum Tunneling through a Potential Barrier .
2.3.1 Electron Tunneling through an Electron Barrier.
2.3.2 Hole Tunneling through a Hole Barrier.
2.3.3 Electron Tunneling from a Trap in the Oxide Gap to the
3.6 New Reliability Issues for 100 or sub 100 nm Technology