Introductory (mini-) CPU design
Mr. Guan Zhi-Yuan is a USTC 7761er (entered USTC with the 4th place in the 1977 Guangdong Province University Entrance Examination). He received his BSEE from USTC in 1982, MSEE from University of Southern California in 1985 and M.Phil in EE (finished Ph.D. all requirement except thesis) from Columbia University in 1996. Mr. Guan Zhi-Yuan is a veteran technology entrepreneur with 27 years of experience in variety of startups in Silicon Valley, including Chief Engineer of Intelligent Signal Technology Corp., Co-Founder and CTO of ElectriPHY Corp., VP of DSP Engineering of DigiCom System, Technical Director of Modem Development in TV/Com International, Snr MTS of Philips Lab. Principal Engineer of General DataComm, MTS of Highspeed Communications,and Independent DSP/Communication Consultant etc.
The (mini-) CPU design course includes quick review of logic design and Verilog modeling and synthesis in FPGA, Instruction Set Architecture, practical methods of CPU design, single cycle PIC16F54 design, Interrupt addition, assembly code and Verilog code co-design and co-verification, real testing in the FPGA board for simple applications, speed optimization for CPU in FPGA, and in the last, introduction to pipeline CPU design. The key feature of this course is to teach students build a complete CPU and its application with S/W development.